A semiconductor memory cell comprises a storage device for to store data and an access device for to access the data stored in the storage device. Capacitors, magnetic junction elements, ferroelectric polarization elements and phase change elements are types of storage devices used in semiconductor memory cells.
In capacitors data is stored by capacitor's charge or lack of charge. In magnetic junction elements data is stored by alignment of the magnetization of a ferromagnetic storage layer with reference to the magnetization of a ferromagnetic reference layer.
Storage devices may be located on top of the access devices. Typically field-effect access transistors (FETs) are used as access devices.
An active area of the access transistor is formed in a single crystalline semiconductor substrate. The active area comprises a first doped region defining a first source/drain-region, a second doped region defining a second source/drain-region and a channel region between the first and the second source/drain-region. The first and the second doped region have a first conductivity type. The channel region is not doped or is of a second conductivity type, which is contrary to the first conductivity type.
In a vertical channel access transistor the first doped region is buried in the semiconductor substrate and coupled to a buried bit line. The bit line transmits data to and from the memory cell. The second doped region is formed adjacent to an upper surface of the substrate and is coupled to the storage device.
Spacer type gate structures or wrap-around type gate structures are provided to achieve high cell packaging densities.
The respective gate structure is formed adjacent to the channel region. A gate dielectric insulates the gate structure from the channel region.
By applying a voltage higher than a threshold voltage to the gate structure a conductive channel is formed in the channel region between the first and the second doped regions. The conductive channel connects the storage device to the bit line. Otherwise, the storage device remains insulated from the bit line.
FIG. 14A is a plan view of a memory cell array with a plurality of memory cells according to prior art. Each memory cell comprises a stacked capacitor and a vertical channel access transistor in a wrap-around type gate spacer layout.
The memory cells are disposed in rows 72 and columns 73. Active areas 6 of vertical channel access transistors 71 are formed in pillars 16 extending outwardly from a bulk section 15 of semiconductor substrate 1. Stacked storage capacitors 83 are disposed on top of active areas 6. Insulating structures 42 separate active areas 6 of neighboring rows 72. Wrap around type gate structures 43 are formed on the sidewalls of active areas 6. The gate structures 43 of adjacent access transistors 71 of each row 72 are coupled to each other and form word lines 41. The word lines 41 extend along the rows 72. The insulating structures 42 separate the word lines 41 of neighboring rows 72 from one another.
FIG. 14B is a cross-section of the layout of FIG. 14A along section line B-B. Stacked capacitors 83 having a bottom electrode 831, a top electrode 833, and a dielectric layer 832 there between are disposed on top of the active areas 6. Each bottom electrode 831 is connected to a contact plug 834. The contact plugs 834 extend downwards to a portion of the respective active area 6. A second doped region 62 is formed in the active area 6 adjacent to the contact plug 834. An interlayer dielectric 46 is provided to separate contact plugs 834.
Bit lines 2 are buried in the semiconductor substrate 1 extending along columns 73 and running perpendicular to rows 72. Each bit line 2 is coupled to first doped regions 61 of the active areas 6 of access transistors 71 disposed along the respective column 73. The first doped regions 61 are formed below the second doped regions 62. A channel region 63 separates each first doped region 61 from the respective second doped region 62.
When spacer gate 43 is activated, access transistor 71 conducts and charges or discharges storage capacitor 83 in accordance with data on the buried bit line 2.
Transistor arrays of this type are described in U.S. Pat. No. 6,504,201, U.S. Pat. No. 6,355,520 B1 and U.S. Patent Application Ser. No. 20030205740.
In each of the patent documents cited above, the buried bit lines are provided by an ion implantation resulting in doped line structures within the single crystalline semiconductor substrate. The active areas are formed on top of the bit lines, such that the first doped region merge to some extend in the bit lines and a low contact resistance between the bit lines and the active areas is achieved.
Buried bit lines formed by implants into the semiconductor substrate suffer from high electric resistance due to limitations for the implanted dopant concentration and general semiconductor properties. A resistivity of lower than 5*10−4 Ωcm cannot be achieved.
With shrinking feature seize a need exists for an improved high density packaging layout for an access transistor array that provides lower bit line resistance and improved cell performance.
Further the layout as described above suffers from the separation of the channel region from the bulk section of the substrate, which results in an accumulation of minority charge carriers in the channel region. The accumulated minority carriers deteriorate the cell characteristics.
Another need exists therefore for a vertical channel access transistor array with channel regions coupled to the bulk sections of the substrate to avoid floating-gate effects.
A further need exists for a method for fabricating access transistor arrays with vertical channel access transistors with bit lines having low electric resistance and with channel regions being coupled to the bulk substrate.